LOGIC_GATES_23_OCTOBER_2022_COPY
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LOGIC_GATES
This web page provides a high level explanation of what basic logic gates are (i.e. AND, OR, and NOT). A logic gate is a component of electronic circuits which maps specific input voltages to specific output voltages (and those voltages are either “low voltage” (i.e. 0) or else “high voltage” (i.e. 1)). For more information on how binary digits can be used to represent verbatim transmittable data, see the BITS_AND_BYTES and HEXIDECIMAL_COLOR_CODE JavaScript single web page application examples in this website.
Note that the term “low voltage” is a classification of voltage levels which are not sufficiently high enough for an electrical current traveling through the wires of an electronic circuit to be detected by a sensor inside of that circuit. Hence, a “low voltage” signal is represented by the binary digit 0 (which means that an insufficient amount of electricity is flowing past the detector for an “on” signal to be observed) by that detector. By contrast, the term “high voltage” is a classification of voltage levels which are sufficiently high enough for an electrical current traveling through the wires of an electronic circuit to be detected by a sensor inside of that circuit. Hence, a “high voltage” signal is represented by the binary digit 1 (which means that a sufficient amount of electricity is flowing past the detector for an “on” signal to be observed by that detector (and what is not an “on” signal is treated as an “off” signal by that detector)).
The following statements enumerate all the permutations of the logic gates named AND, OR, and NOT. (In the context of electronic circuits, AND is represented by a series circuit, OR is represented by a parallel circuit, and NOT is represented by an inverter).
AND(0,0) = 0.
AND(0,1) = 0.
AND(1,0) = 0.
AND(1,1) = 1.
OR(0,0) = 0.
OR(0,1) = 1.
OR(1,0) = 1.
OR(1,1) = 1.
NOT(0) = 1.
NOT(1) = 0.
AND(A,B) = C
The following images depict each possible configuration of an AND gate.
When the input signal named A is “low voltage” (i.e. 0) and the input signal named B is “low voltage” (i.e. 0), the output signal named C is “low voltage” (i.e. 0).
logic_gate_configuration: AND(0,0) = 0.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/AND(0%2C0)_circuit.png
When the input signal named A is “low voltage” (i.e. 0) and the input signal named B is “high voltage” (i.e. 1), the output signal named C is “low voltage” (i.e. 0).
logic_gate_configuration: AND(0,1) = 0.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/AND(0%2C1)_circuit.png
When the input signal named A is “high voltage” (i.e. 1) and the input signal named B is “low voltage” (i.e. 0), the output signal named C is “low voltage” (i.e. 0).
logic_gate_configuration: AND(1,0) = 0.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/AND(1%2C0)_circuit.png
When the input signal named A is “high voltage” (i.e. 1) and the input signal named B is “high voltage” (i.e. 1), the output signal named C is “high voltage” (i.e. 1).
logic_gate_configuration: AND(1,1) = 1.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/AND(1%2C1)_circuit.png
OR(A,B) = C
The following images depict each possible configuration of an OR gate.
When the input signal named A is “low voltage” (i.e. 0) and the input signal named B is “low voltage” (i.e. 0), the output signal named C is “low voltage” (i.e. 0).
logic_gate_configuration: OR(0,0) = 0.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/OR(0%2C0)_circuit.png
When the input signal named A is “low voltage” (i.e. 0) and the input signal named B is “high voltage” (i.e. 1), the output signal named C is “high voltage” (i.e. 1).
logic_gate_configuration: OR(0,1) = 1.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/OR(0%2C1)_circuit.png
When the input signal named A is “high voltage” (i.e. 1) and the input signal named B is “low voltage” (i.e. 0), the output signal named C is “high voltage” (i.e. 1).
logic_gate_configuration: OR(1,0) = 1.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/OR(1%2C0)_circuit.png
When the input signal named A is “high voltage” (i.e. 1) and the input signal named B is “high voltage” (i.e. 1), the output signal named C is “high voltage” (i.e. 1). (Note that the electrical current splits and travels across both wires of the parallel circuit when both switches are closed).
logic_gate_configuration: OR(1,1) = 1.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/OR(1%2C1)_circuit.png
NOT(A) = B
The following images depict each possible configuration of a NOT gate.
When the input signal named A is “low voltage” (i.e. 0), the output signal named B is “high voltage” (i.e. 1). (Note that the NOT gate is a transistor which connects four wires such that the right wire transmits the input signal from switch A, the top wire transmits the inverted signal from A as output, and the left and bottom wires keep the transistor supplied with a constant stream of electricity).
logic_gate_configuration: NOT(0) = 1.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/NOT(0)_circuit.png
When the input signal named A is “high voltage” (i.e. 1), the output signal named B is “low voltage” (i.e. 0). (Note that the NOT gate is a transistor which connects four wires such that the right wire transmits the input signal from switch A, the top wire transmits the inverted signal from A as output, and the left and bottom wires keep the transistor supplied with a constant stream of electricity).
logic_gate_configuration: NOT(1) = 0.
image_link: https://github.com/karlinarayberinger/karlina_object_ultimate_starter_pack/blob/main/NOT(1)_circuit.png
This web page was last updated on 18_OCTOBER_2022. The content displayed on this web page is licensed as PUBLIC_DOMAIN intellectual property.
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This web page was last updated on 23_OCTOBER_2022. The content displayed on this web page is licensed as PUBLIC_DOMAIN intellectual property.
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